Digital-to-analog converters are widely used for converting digital signals to corresponding analog signals for many electronic circuits. For example, a high resolution, high speed digital-to-analog converter (DAC) may find applications in cellular base stations, wireless communications, direct digital frequency synthesis, signal reconstruction, test equipment, high resolution imaging systems and arbitrary waveform generators, for example.
An integrated circuit DAC is described, for example, in U.S. Pat. No. 3,961,326 to Craven entitled "Solid State Digital to Analog Converter". The DAC includes binarily scaled constant current sources with associated switch cells employing bipolar transistors to direct the bit currents either to a current summing bus or to ground. Unfortunately, the DAC may be susceptible to errors as caused by switching glitches. In addition, the current sources may have values which differ from the intended value. The current sources may be non-uniform for various reasons, such as circuit layout mismatch, thermal distribution, and/or process variations.
There have been attempts to further reduce glitch, for example, in a DAC and thereby reduce harmonic distortion and other undesired signals in the output spectrum. For example, a DAC for video applications is disclosed in an article entitled "A Low Glitch 10-bit 75-MHz CMOS Video D/A Converter" by Wu et al. in the IEEE Journal of Solid-State Circuits, Vol. 30, No. 1, January 1995. The DAC includes a segmented anti-symmetric switching sequence and an asymmetrical switching buffer. The DAC includes a large number of non-weighted current sources for the seven most significant bits, and weighted current sources for the three least significant bits.
Another DAC is disclosed in an article by Bastiaansen et al. entitled "A 10-b 40-MHz 0.8-um CMOS Current-Output D/A Converter" in IEEE Journal of Solid-State Circuits, Vol. 26, No. 7, July 1991. The DAC is based on current division and current switching. Monotonicity of the converter requires that the integral non-linearity (INL) be less than .+-.0.5 LSB. Unfortunately, this places high demands on upon the matching of the current sources. An article entitled "A 16-b D/A Converter with Increased Spurious Free Dynamic Range" by Mercer in the IEEE Journal of Solid-State Circuits, Vol. 29, No. 10, October 1994, pp. 1180-1185 discloses another DAC. The article identifies the two broad categories of errors or distortion in digital-to-analog conversion. Segmentation of the bits and laser trimming of thin film resistors are often used to minimize static errors. Dynamic or AC errors include nonlinear settling, ringing, non-symmetric slew, and glitch. Thermometer decoding of the most significant bits along with high-speed process technologies are often employed to minimize the dynamic errors. Segmentation of the four most significant bits into 15 currents of equal size is disclosed. Laser trimmable thin-film resistors are used in the DAC current sources to allow trimming to reduce linearity errors.
Unfortunately, despite continued improvements in DAC operating speed and accuracy, factors may still significantly effect the linearity of the DAC. For example, non-uniformity of the current sources may adversely affect the linearity of the DAC. One approach to achieve higher accuracy will suffer a reduced die yield. Unfortunately, the cost of each DAC may be greatly increased as yields are reduced.